Embedded systems for IT security applications: properties and design considerations
Proceedings of the 2nd international conference on Security of information and networks
An efficient implementation of montgomery powering ladder in reconfigurable hardware
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
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We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.