A new low latency parallel turbo decoder employing parallel phase decoding method

Authors:
Wen-Ta Lee;Min-Sheng Chang;Wei-Chieh Shen
Affiliations:
Institute of Computer and Communication, National Taipei University of Technology, Taipei, Taiwan;Institute of Computer and Communication, National Taipei University of Technology, Taipei, Taiwan;Institute of Computer and Communication, National Taipei University of Technology, Taipei, Taiwan
Venue:
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Year:
2012

Citing 4
Cited 0

Low-Latency Turbo Decoder Design by Concurrent Decoding of Component Codes

ICICIC '08 Proceedings of the 2008 3rd International Conference on Innovative Computing Information and Control
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)

IEEE Transactions on Information Theory
An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes

IEEE Journal on Selected Areas in Communications

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a new parallel phase algorithm for parallel turbo decoder is proposed. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. For verifying the proposed parallel phase turbo decoder, we have used FPGA to emulate the hardware architectures, and designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS process. The gate count of this decoder chip is 128284. The chip size including I/O pad is 1.91×1.91mm2. The simulation result shows that, compared to traditional sliding window method, for different code size, parallel phase turbo decoding method has 51.23%~58.13% decoding time saved, with 8 iteration times at 100MHz working frequency.