Fundamentals of interactive computer graphics
Fundamentals of interactive computer graphics
On the power of the frame buffer
ACM Transactions on Graphics (TOG)
A display system for the Stellar graphics supercomputer model GS1000
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Near Real-Time CSG Rendering Using Tree Normalization and Geometric Pruning
IEEE Computer Graphics and Applications
Transparency and Antialiasing Algorithms Implemented with the Virtual Pixel Maps Technique
IEEE Computer Graphics and Applications
The Silicon Graphics 4D/240GTX Superworkstation
IEEE Computer Graphics and Applications
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Contemporary graphics architectures are based on a hardware-supported geometric pipeline, a rasterizer, a z-buffer and two frame buffers. Additional pixel memory is used for alpha blending and for storing logical information. Although their functionality is growing it is still limited because of the fixed use of pixel memory and the restricted set of operations provided by these architectures. A new class of graphics algorithms that considerably extends the current technology is based on a more flexible use of pixel memory, not supported by current architectures. The M-Buffer architecture described here divides pixel memory into general-purpose buffers, each associated with one processor. Pixel data is broadcast to all buffers simultaneously. Logical and numeric tests are performed by each processor and the results are broadcast and used by all buffers in parallel to evaluate logical expressions for the pixel update condition. The architecture is scalable by addition of buffer-processors, suitable for pixel parallelization, and permits the use of buffers for different purposes. The architecture, its functional description, and a powerful programming interface are described.