Parallel fixed point digital differential analyzer

Authors:
Ramón P. Mollá;Ricardo Quirós;Javier Lluch;Roberto Vivó
Affiliations:
Sección de Informáica Gráfica, Departamento de Sistemas Informáticos y Computación, Universidad Politecnica de Valencia, Valencia, Spain;Sección de Informáica Gráfica, Departamento de Sistemas Informáticos y Computación, Universidad Politecnica de Valencia, Valencia, Spain;Sección de Informáica Gráfica, Departamento de Sistemas Informáticos y Computación, Universidad Politecnica de Valencia, Valencia, Spain;Sección de Informáica Gráfica, Departamento de Sistemas Informáticos y Computación, Universidad Politecnica de Valencia, Valencia, Spain
Venue:
EGGH'93 Proceedings of the Eighth Eurographics conference on Graphics Hardware
Year:
1993

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Abstract

Two main serial algorithms to scan convert straight lines have been proposed: Bresenham and Digital Differential Analyzer. The Bresenham algorithm has became a standard because of integer arithmetic. Many theoretical solutions have been proposed to parallelize Bresenham algorithm but its implementation is difficult. So most parallelizations take advantage of repeated patterns, massive parallel computers and so on. Sequential Digital Differential Analyzer shows better peformance than Bresenham if fixed point arithmetic is used. This algorithm can be pipe lined and parallelized. It is easily hardware implemented and scalable. Hardware cost is linear with speed up. Utilization is nearly 100% and hardware waste is low.