Procedural elements for computer graphics
Procedural elements for computer graphics
Ray tracing parametric surface patches utilizing numerical techniques and ray coherence
SIGGRAPH '86 Proceedings of the 13th annual conference on Computer graphics and interactive techniques
On speeding up ray tracing of B-spline surfaces
Computer-Aided Design
A simple, general method for ray tracing bicubic surfaces
CG International '87 on Computer graphics 1987
The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches
IEEE Computer Graphics and Applications
Ray tracing rational B-spline patches in VLSI
Advances in computer graphics hardware II
Ray tracing parametric surfaces by subdivision in viewing plane
Theory and practice of geometric modeling
Ray tracing trimmed rational surface patches
SIGGRAPH '90 Proceedings of the 17th annual conference on Computer graphics and interactive techniques
On ray tracing parametric surfaces
SIGGRAPH '85 Proceedings of the 12th annual conference on Computer graphics and interactive techniques
Scan line methods for displaying parametrically defined surfaces
Communications of the ACM
VLSI Chip for Ray Tracing Bicubic Patches
Advances in Computer Graphics Hardware I (Eurographics'86 Workshop)
Ray tracing parametric patches
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
A fast scan-line algorithm for rendering parametric surfaces
SIGGRAPH '79 Proceedings of the 6th annual conference on Computer graphics and interactive techniques
Ray Tracing Free-Form B-Spline Surfaces
IEEE Computer Graphics and Applications
A Theoretical Development for the Computer Generation and Display of Piecewise Polynomial Surfaces
IEEE Transactions on Pattern Analysis and Machine Intelligence
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A new fast ray - patch intersection algorithm is presented. The algorithm correctly handles all ray - patch intersections. A number of parameters are derived from a numerical analysis of the algorithm and the data pad is re synthesized for higher accuracy. A global architecture for an ASIC for intersecting a ray with a bezier patch is presented. It is shown that a cache combined with pre pads can reduce the required memory considerable with an extremely small performance penalty. Attention will be paid to the scheduling and control problem. Several high level optimizations are presented that make efficient scheduling possible and decrease the calculation time considerably.