Amortized efficiency of list update and paging rules
Communications of the ACM
Approximating total flow time on parallel machines
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
Online computation and competitive analysis
Online computation and competitive analysis
Competitve buffer management for shared-memory switches
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Dynamic routing on networks with fixed-size buffers
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
Predictive scheduling of network processors
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
A pipelined memory architecture for high throughput network processors
Proceedings of the 30th annual international symposium on Computer architecture
Buffer Overflow Management in QoS Switches
SIAM Journal on Computing
Harmonic buffer management policy for shared memory switches
Theoretical Computer Science - Special issue: Online algorithms in memoriam, Steve Seiden
Online Scheduling to Minimize Average Stretch
SIAM Journal on Computing
On the Performance of Greedy Algorithms in Packet Buffering
SIAM Journal on Computing
Performance/area efficiency in chip multiprocessors with micro-caches
Proceedings of the 4th international conference on Computing frontiers
Competitive online scheduling for server systems
ACM SIGMETRICS Performance Evaluation Review
Maximizing throughput in multi-queue switches
Algorithmica
PAM: a novel performance/power aware meta-scheduler for multi-core systems
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
A remotely accessible network processor-based router for network experimentation
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A study on optimally co-scheduling jobs of different lengths on chip multiprocessors
Proceedings of the 6th ACM conference on Computing frontiers
Throughput loss in task scheduling due to server state uncertainty
Proceedings of the Fourth International ICST Conference on Performance Evaluation Methodologies and Tools
Addressing shared resource contention in multicore processors via scheduling
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
A hardware packet re-sequencer unit for network processors
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
A folded pipeline network processor architecture for 100 Gbit/s networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
| Hi-index | 0.00 |
Current network processors (NPs) increasingly deal with packets with heterogeneous processing times. In such an environment, packets that require many processing cycles delay low-latency traffic because the common approach in today's NPs is to employ run-to-completion processing. These difficulties have led to the emergence of the Multipass NP architecture, where after a processing cycle ends, all processed packets are recycled into the buffer and recompete for processing resources. In this paper, we provide a model that captures many of the characteristics of this architecture, and we consider several scheduling and buffer management algorithms that are specially designed to optimize the performance of multipass network processors. In particular, we provide analytical guarantees for the throughput performance of our algorithms. We further conduct a comprehensive simulation study, which validates our results.