Design of a low power wide-band high resolution programmable frequency divider
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A synchronous 50% duty-cycle clock generator in 0.35-µm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work presents a full-division-range programmable frequency divider with 50% duty-cycle output. The proposed programmable frequency divider includes a programmable counter (PC) and duty-cycle-improved circuit (DCIC) to achieve full-division-range, low-area, and close-to-50% duty-cycle output from an input clock with an arbitrary duty cycle. A chip was fabricated using 0.18-@mm standard CMOS process with a 1.8-V power supply. The experimental results show that the proposed programmable frequency divider can operate correctly when input clock frequency ranges from 1MHz to 1GHz and division ratio ranges from 1 to 63. For an input divisor of 20 with input clock frequencies of 700 and 1MHz and duty cycles of 20% and 99.5%, the output duty cycles were 50.4% and 50%, respectively. The total power consumption of the proposed programmable frequency divider was only 0.62mW at 700MHz, and the active die area was only 0.125x0.05mm^2.