De-blocking filter design for HEVC and H.264/AVC

Authors:
Muchen Li;Jinjia Zhou;Dajiang Zhou;Xiao Peng;Satoshi Goto
Affiliations:
The Graduate School of Information, Production and Systems, Waseda University, Japan;The Graduate School of Information, Production and Systems, Waseda University, Japan;The Graduate School of Information, Production and Systems, Waseda University, Japan;The Graduate School of Information, Production and Systems, Waseda University, Japan;The Graduate School of Information, Production and Systems, Waseda University, Japan
Venue:
PCM'12 Proceedings of the 13th Pacific-Rim conference on Advances in Multimedia Information Processing
Year:
2012

Citing 6
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Abstract

As the successor of H.264/AVC, HEVC inherits the basic property of H.264/AVC and gives some new features. This paper introduces a novel dual-standard de-blocking filter architecture which could support both of the HEVC and H.264/AVC standards. It takes 48 clock cycles for H.264/AVC and 24 cycles for HEVC for every 16×16 block. The proposed unified-cross based processing order greatly reduces the design complexity. The proposed architecture occupies 43.3k equivalent gate count at frequency of 200MHz in SMIC 65nm library, which could satisfy the throughput requirement of quad-full high definition (QFHD) on 60fps for H.264/AVC and super hi-vision (SHV) on 60fps for HEVC. In addition, the total power consumption could be reduced by 37.8% in skipping mode when the edges need not be filtered.