Runtime elision of transactional barriers for captured memory

Authors:
Fernando Miguel Carvalho;João Cachopo
Affiliations:
Lisbon Polytechnic Institute (ISEL), Lisbon, Portugal;Technical University of Lisbon, Lisbon, Portugal
Venue:
Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming
Year:
2013

Citing 6
Cited 0

STMBench7: a benchmark for software transactional memory

Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007
Kicking the tires of software transactional memory: why the going gets tough

Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
Optimizing transactions for captured memory

Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
Lowering STM overhead with static analysis

LCPC'10 Proceedings of the 23rd international conference on Languages and compilers for parallel computing
Transactional locking II

DISC'06 Proceedings of the 20th international conference on Distributed Computing
A lazy snapshot algorithm with eager validation

DISC'06 Proceedings of the 20th international conference on Distributed Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose a new technique that can identify transaction-local memory (i.e. captured memory), in managed environments, while having a low runtime overhead. We implemented our proposal in a well known STM framework (Deuce) and we tested it in STMBench7 with two different STMs: TL2 and LSA. In both STMs the performance improved significantly (4 times and 2.6 times, respectively). Moreover, running the STAMP benchmarks with our approach shows improvements of 7 times in the best case for the Vacation application.