Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
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Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
A flexible framework for implementing software transactional memory
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Conflict detection and validation strategies for software transactional memory
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A lazy snapshot algorithm with eager validation
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Adaptive software transactional memory
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Transactions are back---but are they the same?
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CAR-STM: scheduling-based collision avoidance and resolution for software transactional memory
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Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory
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On Replication of Software Transactional Memories
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Atomic quake: using transactional memory in an interactive multiplayer game server
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WormBench: a configurable workload for evaluating transactional memory systems
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QuakeTM: parallelizing a complex sequential application using transactional memory
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Refereeing conflicts in hardware transactional memory
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Stretching transactional memory
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Preventing versus curing: avoiding conflicts in transactional memories
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On the Impact of Serializing Contention Management on STM Performance
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Extensible transactional memory testbed
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Implementation tradeoffs in the design of flexible transactional memory support
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Memoization of methods using software transactional memory to track internal state dependencies
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A study of transactional memory vs. locks in practice
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Parallelizing a real-time physics engine using transactional memory
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SMV: selective multi-versioning STM
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LUTS: a lightweight user-level transaction scheduler
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STM with transparent API considered harmful
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Profiling and tuning the performance of an STM-based concurrent program
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A lock-free cache invalidation protocol for the atom system
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Runtime elision of transactional barriers for captured memory
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Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse-grained locking and easier to use than fine-grained locking. However, STM implementations have yet to demonstrate that their runtime overheads are acceptable. To date, empiric evaluations of these implementations have suffered from the lack of realistic benchmarks. Measuring performance of an STM in an overly simplified setting can be at best uninformative and at worst misleading as it may steer researchers to try to optimize irrelevant aspects of their implementations. This paper presents STMBench7: a candidate benchmark for evaluating STM implementations. The underlying data structure consists of a set of graphs and indexes intended to be suggestive of many complex applications, e.g., CAD/CAM. A collection of operations is supported to model a wide range of workloads and concurrency patterns. Companion locking strategies serve as a baseline for STM performance comparisons. STMBench7 strives for simplicity. Users may choose a workload, number of threads, benchmark length, as well as the possibility of structure modification and the nature of traversals of shared data structures. We illustrate the use of STMBench7 with an evaluation of a well-known software transactional memory implementation.