Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
EURASIP Journal on Applied Signal Processing
Journal of Signal Processing Systems
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV
Proceedings of the 21st annual symposium on Integrated circuits and system design
ICASSP '09 Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing
A power-efficient and self-adaptive prediction engine for H.264/AVC decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Consumer Electronics
A novel VLSI architecture of motion compensation for multiple standards
IEEE Transactions on Consumer Electronics
The H.264/MPEG4 advanced video coding standard and its applications
IEEE Communications Magazine
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This article presents the HP422-MoCHA: optimized Motion Compensation hardware architecture for the High 4:2:2 profile of H.264/AVC video coding standard. The proposed design focuses on real-time decoding for HDTV 1080p (1,920 脳 1,080 pixels) at 30 fps. It supports multiple sample bit-width (8, 9, or 10 bits) and multiple chroma sub-sampling formats (4:0:0, 4:2:0, and 4:2:2) to provide enhanced video quality experience. The architecture includes an optimized sample interpolator that processes luma and chroma samples in two parallel datapaths and features quarter sample accuracy, bi-prediction and weighted prediction. HP422-MoCHA also includes a hardwired Motion Vector Predictor, supporting temporal and spatial direct predictions. A novel memory hierarchy implemented as a 3-D Cache reduces the frame memory access, providing, on average, 62% of bandwidth and 80% of clock cycles reduction. The design was implemented in a Xilinx Virtex-II PRO FPGA, and also in an ASIC with a TSMC 0.18 μm standard cells technology. The ASIC implementation occupies 102 K equivalent gates and 56.5 KB of on-chip SRAM in a 3.8 脳 3.4 mm2 area. It presents a power consumption of 130 mW. Both implementations reach a maximum operation frequency of ~100 MHz, being able to motion compensate 37 bi-predictive frames or 69 predictive fps. The minimum required frequency to ensure the real-time decoding for HD1080p at 30 fps is 82 MHz. Since HP422-MoCHA is the first Motion Compensation architecture for the High 4:2:2 profile found in the literature, a Main profile MoCHA was used for comparison purposes, showing the highest throughput among all presented works. However, the HP422-MoCHA architecture also reaches the highest throughput when compared with the other published Main profile MC solutions, even considering the significantly higher complexity of the High 4:2:2 profile.