An interpolating digitally controlled oscillator for a wide-range all-digital PLL
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm
IEEE Transactions on Circuits and Systems II: Express Briefs
A fast locking all-digital phase-locked loop via feed-forward compensation technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL
Analog Integrated Circuits and Signal Processing
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This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9---7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of