RF microelectronics
IEEE Transactions on Circuits and Systems Part I: Regular Papers
PLL performance comparison with application to spread spectrum clock generator design
Analog Integrated Circuits and Signal Processing
A low-power quadrature VCO and its application to a 0.6-V 2.4-Ghz PLL
IEEE Transactions on Circuits and Systems Part I: Regular Papers
CMOS Circuit Design, Layout, and Simulation
CMOS Circuit Design, Layout, and Simulation
Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS
Analog Integrated Circuits and Signal Processing
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The design details of a low power/wide tuning range phase locked loop (PLL) is presented in 180 nm CMOS together with the simulated and post fabrication measured performance. The PLL has been specifically designed for applications requiring a wide tuning range (1.55---2.28 GHz) while maintaining low power consumption (18 mW) and good phase noise (驴100.9 dBc/Hz at 1 MHz). The tuning range represents significant improvement over other reported PLL CMOS implementations. To illustrate the robustness of the architecture, a 90 nm CMOS design is included with a 5.8---9.45 GHz tuning range (48%), phase noise of 驴111.7 dBc/Hz, and power consumption of 18.6 mW. The stand alone voltage controlled oscillator (VCO) and the PLL were fabricated on a single 180 nm die providing a unique opportunity to analyze and measure both the stand alone VCO phase noise performance and the integrated PLL phase noise performance. The contributions to the PLL phase noise (phase detector, charge pump, VCO, divider, and reference source) are delineated and both the theoretical and measured PLL phase noise performance is discussed. Design tradeoffs are included such as effect of loop bandwidth on phase noise contributions.