A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors

Authors:
Ping-Yuan Deng;Jean-Fu Kiang
Affiliations:
Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan;Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

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Abstract

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-µm CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18mW of power, of which only 3.93mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of -104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm × 0.95 mm.