Sinusoidal shaping of the ISF in LC oscillators
International Journal of Circuit Theory and Applications
Wideband multi-mode CMOS VCO design using coupled inductors
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
IEEE Transactions on Circuits and Systems Part I: Regular Papers
LC-active VCO for CMOS RF transceivers
International Journal of Circuit Theory and Applications
International Journal of Circuit Theory and Applications
The effect of parameter mismatches on the output waveform of an LC-VCO
International Journal of Circuit Theory and Applications
Experimental comparison of phase-noise in cross-coupled RC- and LC-oscillators
International Journal of Circuit Theory and Applications
Hi-index | 12.05 |
This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is -121.6dBc/Hz at 1MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1mW. The chip with an area of 1.048x1.076mm^2 is fabricated in a TSMC 0.18@mm CMOS 1P6M technology process.