A reference-free 7-bit 500 MS/s pipeline ADC using current-mode reference shifting and quantizers with built-in thresholds

Authors:
Michael Figueiredo;Edinei Santin;João Goes;Guiomar Evans;Nuno Paulino
Affiliations:
Department of Electrical Engineering, Faculty of Sciences and Technology, Centre of Technology and Systems (UNINOVA-CTS), Universidade Nova de Lisboa, Caparica, Portugal 2829-516;Department of Electrical Engineering, Faculty of Sciences and Technology, Centre of Technology and Systems (UNINOVA-CTS), Universidade Nova de Lisboa, Caparica, Portugal 2829-516;Department of Electrical Engineering, Faculty of Sciences and Technology, Centre of Technology and Systems (UNINOVA-CTS), Universidade Nova de Lisboa, Caparica, Portugal 2829-516 and S3-Group, Mad ...;Departamento de Física, The Centro de Física da Matéria Condensada, Faculdade de Ciências da, Universidade de Lisboa, Lisbon, Portugal 1749-016;Department of Electrical Engineering, Faculty of Sciences and Technology, Centre of Technology and Systems (UNINOVA-CTS), Universidade Nova de Lisboa, Caparica, Portugal 2829-516 and S3-Group, Mad ...
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2013

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Abstract

The pursuit for energy and area efficient circuits has become greater than ever. Low power and small area integrated circuits are in high demand today. Reference voltage circuitry for analog-to-digital conversion comprises 20---30 % of the overall power and area of the ADC. To this end, a fully differential 1.5-bit multiplying digital-to-analog converter (MDAC) precluding reference voltages, that can be employed in MDAC-based ADCs, is presented. Reference shifting is performed in current-mode and the gain of two is obtained by associating charged capacitors in series in the opamp's feedback loop, achieving a unity feedback factor. Theoretical analyses of various nonideal effects of the reference shifting and gain of two are presented and confirmed with electrical level simulations. Furthermore, to avoid reference voltages in the local quantizers, an architecture with built-in thresholds is used. A proof of concept 1.5-bit/stage 7-bit 500 MS/s pipeline ADC is designed using the proposed MDAC in a standard digital 0.13 μm CMOS technology. The ADC achieves a peak SNDR and SFDR of 36.1 and 48.7 dB, respectively, while dissipating 12.7 mW from a single 1.2 V supply voltage, and it does not require external reference circuitry.