Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters

Authors:
Yun Pan;Ning Zheng;Qinglin Tian;Xiaolang Yan;Ruohong Huan
Affiliations:
Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, China;Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, China;College of Electrical Engineering, Zhejiang University, Hangzhou, China;College of Electrical Engineering, Zhejiang University, Hangzhou, China;College of Computer Science and Technology, Zhejiang University of Technology, Hangzhou, China
Venue:
Journal of Signal Processing Systems
Year:
2013

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Abstract

In this paper, we introduce a hierarchical resampling (HR) algorithm and architecture for distributed particle filters (PFs). While maintaining the same accuracy as centralized resampling in statistics, the proposed HR algorithm decomposes the resampling step into two hierarchies including intermediate resampling (IR) and unitary resampling (UR), which suits PFs for distributed hardware implementation. Also presented includes a residual cumulative resampling (RCR) method that pipelines and accelerates the UR step. The corresponding architecture, when compared with traditional distributed architectures, eliminates the particle redistribution step, and has such advantages as short execution time and high memory efficiency. The prototype containing 8 PEs has been developed in Xilinx Virtex IV FPGA (XC4VFX100-12FF1152) for the bearings-only tracking (BOT) problem, and the result shows that the input observations can be processed at 37.21 KHz with 8 K particles and a clock speed of 80 MHz.