Harpoon: a flow-level traffic generator for router and network tests
Proceedings of the joint international conference on Measurement and modeling of computer systems
Design of a High Performance Traffic Generator on Network Processor
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
NetCOPE: Platform for Rapid Development of Network Applications
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Do you trust your software-based traffic generator?
IEEE Communications Magazine
Hacking NetCOPE to Run on NetFPGA-10G
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Flexible high performance traffic generation on commodity multi---core platforms
TMA'12 Proceedings of the 4th international conference on Traffic Monitoring and Analysis
Caliper: Precise and Responsive Traffic Generator
HOTI '12 Proceedings of the 2012 IEEE 20th Annual Symposium on High-Performance Interconnects
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As high-speed links become ubiquitous in current networks, testing new algorithms at high speed is essential for researchers. This task often makes it necessary to generate traffic with some specified features : distribution of packet sizes, payload content, number of TCP or UDP flows, etc. When targeting a data rate of many Gb/s, this cannot be done with commodity computers. Commercial traffic generators exist for this task, but they are expensive and do not fit the precise needs of researchers. In this paper, we describe an open-source implementation of a traffic generator capable of filling a 10 Gb/s Ethernet link, with traffic features specified in software. The implementation works on a board including an FPGA and a 10 Gb/s network interface, like the Combo from INVEA-TECH or the NetFPGA 10G. These boards are affordable for research and can provide a configurable and easily extensible traffic generator.