PacketShader: a GPU-accelerated software router
Proceedings of the ACM SIGCOMM 2010 conference
Do you trust your software-based traffic generator?
IEEE Communications Magazine
On multi---gigabit packet capturing with multi---core commodity hardware
PAM'12 Proceedings of the 13th international conference on Passive and Active Measurement
Flexible, extensible, open-source and affordable FPGA-based traffic generator
Proceedings of the first edition workshop on High performance and programmable networking
From 1G to 10G: code reuse in action
Proceedings of the first edition workshop on High performance and programmable networking
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Generating high-volume and accurate test traffic is crucial for assessing the performance of network devices in a reliable way and under different stress conditions. However, traffic generation still relies mostly on special purpose hardware. In fact, available software generators are able to reproduce rich and involved traffic patterns, but do not meet the performance requirements that are needed for effectively challenging the device under test. Nevertheless, hardware devices usually provide limited flexibility with respect to the traffic patterns that they can generate. The aim of this work is to design a traffic generator which can both achieve good performance and provide a flexible framework for supporting arbitrary traffic models. The key factor that enables our system to meet both requirements is parallelism, which is increasingly provided by modern commodity hardware: indeed our generator, which includes both kernel and user space components, can efficiently scale with multiple cores and multi---queue commodity network cards. By leveraging such a design, our generator is able to produce close-to-line-rate traffic on a 10Gbps link, while accommodating multiple traffic models and providing good accuracy.