Performance modeling using the Motorola PowerPC timing simulator

  • Authors:
  • Tariq Afzal

  • Affiliations:
  • Motorola, RISC Software DivisionAustin, Texas

  • Venue:
  • ACM SIGARCH Computer Architecture News
  • Year:
  • 1995

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Abstract

Published and projected benchmark numbers do not necessarily help predict the behavior of a user application on a particular microprocessor system. The real test comes when a user application is executed and timed on the microprocessor[5], which usually stresses the system in a different fashion than most benchmarks do. Unfortunately, the lack of stable platforms in earlier stages of system design prevents a developer from performing such evaluation tasks. This paper illustrates how application developers looking for a head start can use the Motorola Timing Simulator for the PowerPC 603™ microprocessor to analyze the expected behavior of a user program for various memory subsystems and gather fairly accurate timing information. A study of some SPEC™ benchmarks is also done in this respect.