3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
Proceedings of the 48th Design Automation Conference
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
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In 3D ICs, interlayer communication is achieved using through-silicon-vias (TSVs), which can suffer from cross coupling if placed naïvely. In this paper, cross coupling between TSVs is modeled, and a chip-scale TSV coupling mitigation scheme is presented using TSV shielding. A geometric coupling model is developed which is simple enough to quickly estimate the pairwise coupling between TSVs, unlike circuit models of coupling that have been proposed in previous works. Our geometric model's ability to make fast accurate estimations of chip-scale cross coupling make it a good model to use for shield placement optimization. A shield placement algorithm is presented which reduces TSV coupling by formulating a min cost flow (MCF) problem based on the proposed model. Our algorithm is compared to another shield placement algorithm presented in [9] which is based on a circuit model of coupling. Experimental results show that the algorithm proposed here is able to reduce the total cross coupling in a layout an average of 4.59x more than the other algorithm while using the same number of shields. Alternatively, our algorithm uses an average of 88% less shields to shield a layout to the same degree as the shielding schemes produced by the other algorithm.