Low power 3-D stacking multimedia platform with reconfigurable memory architecture

  • Authors:

  • Po-Han Huang;Huang-Lun Lin;Hsien-Ching Hsieh;Chi-Hung Lin;Shui-An Wen;Yi-Fa Sun

  • Affiliations:

  • Industrial Technology Research Institute, Hsinchu, Taiwan Roc;Industrial Technology Research Institute, Hsinchu, Taiwan Roc;Industrial Technology Research Institute, Hsinchu, Taiwan Roc;Industrial Technology Research Institute, Hsinchu, Taiwan Roc;Industrial Technology Research Institute, Hsinchu, Taiwan Roc;Industrial Technology Research Institute, Hsinchu, Taiwan Roc

  • Venue:
  • Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
  • Year:
  • 2013

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Abstract

In this paper, a low power and high performance three-dimensional (3-D) stacking multimedia platform called "3D-PAC" is proposed. This platform is a heterogeneous integration composed of a low power design logic layer (2D-PAC) and a reconfigurable memory tier via 3-D technology. After extensive 3-D architecture exploration with Electronic System Level (ESL) simulation, there is a 54% performance speedup compared with the former 2-D architecture for certain multimedia applications. This chip is fabricated in TSMC 90nm generic CMOS technology. The area of 2D-PAC is about 7880 x 7880 μm2 and the SRAM layer is about 3880 x 3880 μm2. Both layers are combined with 1,886 TSVs.