Lifetime reliability assessment with aging information from low-level sensors

Authors:
Yao Wang;Sorin D. Cotofana;Liang Fang
Affiliations:
Delft University of Technology, Delft, Netherlands;Delft University of Technology, Delft, Netherlands;National University of Defense Technology, Changsha, China
Venue:
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Year:
2013

Citing 3
Cited 0

The Case for Lifetime Reliability-Aware Microprocessors

Proceedings of the 31st annual international symposium on Computer architecture
Reliability challenges for 45nm and beyond

Proceedings of the 43rd annual Design Automation Conference
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

Aggressive technology scaling has led Integrated Circuits (ICs) suffer from ever-increasing wearout effects. As a consequence, Dynamic Reliability Management (DRM) becomes an essential approach to assure IC's lifetime reliability. Accurate and efficient reliability modeling from low-level aging sensor measurements is critical to DRM systems. This work presents a Time-Sharing Sensing (TSS) method for $V_{th}$-sensor based DRM to assess the dynamic NBTI-induced degradation experienced by the circuit under monitoring. SPICE simulation results suggest that the proposed TSS method can accurately capture the circuit reliability status under random stress conditions.