A fast handshake join implementation on FPGA with adaptive merging network

  • Authors:
  • Yasin Oge;Takefumi Miyoshi;Hideyuki Kawashima;Tsutomu Yoshinaga

  • Affiliations:
  • University of Electro-Communications, Japan;e-trees.Japan, Inc.;University of Tsukuba, Japan;University of Electro-Communications, Japan

  • Venue:
  • Proceedings of the 25th International Conference on Scientific and Statistical Database Management
  • Year:
  • 2013

Quantified Score

Hi-index 0.00

Visualization

Abstract

One of a critical design issues for implementing handshake-join hardware is result collection performed by a merging network. To address the issue, we introduce an adaptive merging network. Our implementation achieves over 3 million tuples per second when the selectivity is 0.1. The proposed implementation attains up to 5.2x higher throughput than original handshake-join hardware. In this demonstration, we apply the proposed technique to filter out malicious packets from packet streams. To the best of our knowledge, our system is the fastest handshake join implementation on FPGA.