An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture

Authors:
Farhat Thabet;Yves Lhuillier;Caaliph Andriamisaina;Jean-Marc Philippe;Raphaël David
Affiliations:
CEA LIST, Embedded Computing Lab, Gif sur Yvette, France;CEA LIST, Embedded Computing Lab, Gif sur Yvette, France;CEA LIST, Embedded Computing Lab, Gif sur Yvette, France;CEA LIST, Embedded Computing Lab, Gif sur Yvette, France;CEA LIST, Embedded Computing Lab, Gif sur Yvette, France
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 5
Cited 2

Algorithms for scalable synchronization on shared-memory multiprocessors

ACM Transactions on Computer Systems (TOCS)
Memory system design for bus-based multiprocessors

Memory system design for bus-based multiprocessors
Architectural Support for Fair Reader-Writer Locking

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
ARTM: a lightweight fork-join framework for many-core embedded systems

Proceedings of the Conference on Design, Automation and Test in Europe
P2012: building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

ARTM: a lightweight fork-join framework for many-core embedded systems

Proceedings of the Conference on Design, Automation and Test in Europe
HARS: A hardware-assisted runtime software for embedded many-core architectures

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, the STMicroelectronics/CEA Platform 2012 (P2012) project designed an area- and power-efficient many-core accelerator as an answer to the needs of computing power of next-generation data-intensive embedded applications. Synchronization handling on this architecture was critical since speed-ups of parallel implementations of embedded applications strongly depend on the ability to exploit the largest possible number of cores while limiting task management overhead. This paper presents the HardWare Synchronizer (HWS), a flexible hardware accelerator for synchronization operations in the P2012 architecture. Experiments on a multi-core test chip showed that the HWS has less than 1% area overhead while reducing synchronization latencies (up to 2.8 times) and contentions.