Memory system design for bus-based multiprocessors

Queuing theoretic model for a multiprocessor with private caches and shared memory

ACM SIGARCH Computer Architecture News

Architectural Support for Fair Reader-Writer Locking

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture

Proceedings of the Conference on Design, Automation and Test in Europe

HARS: A hardware-assisted runtime software for embedded many-core architectures

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers