Capturing vulnerability variations for register files

Authors:
Javier Carretero;Enric Herrero;Matteo Monchiero;Tanausú Ramírez;Xavier Vera
Affiliations:
Intel Barcelona Research Center, Intel Labs;Intel Barcelona Research Center, Intel Labs;Intel Barcelona Research Center, Intel Labs;Intel Barcelona Research Center, Intel Labs;Intel Barcelona Research Center, Intel Labs
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 9
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Abstract

Soft error rates are estimated based on worst-case architectural vulnerability factor (AVF). Therefore, it makes tracking real-time accurate AVF very attractive to computer designers: more accurate AVF numbers will allow turning on more features at runtime while keeping the promised SDC and DUE rates. This paper presents a hardware mechanism based on linear regressions to estimate the AVF (SDC and DUE) of the register file for out-of-order cores. Our results show that we are able to have a high correlation factor at low cost.