PVT variation tolerant current source with on-chip digital self-calibration

Authors:
Moo-Young Kim;Hokyu Lee;Chulwoo Kim
Affiliations:
Electrical and Electronics Engineering Department, Korea University, Seoul, Korea;Electrical and Electronics Engineering Department, Korea University, Seoul, Korea;Electrical and Electronics Engineering Department, Korea University, Seoul, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 1
Cited 1

Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies

Quantified Score

Hi-index	0.00

Visualization

Abstract

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm2 and consumes 94.9µW at a supply voltage of 1.0 V.