A multiphase timing-skew calibration technique using zero-crossing detection
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An antiharmonic, programmable, DLL-based frequency multiplier for dynamic frequency scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A programmable edge-combining DLL with a current-splitting charge pump for spur suppression
IEEE Transactions on Circuits and Systems II: Express Briefs
A DLL design for testing I/O setup and hold times
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents the random jitter and deterministic jitter analysis on the proposed polyphase filter (PPF)-based multiphase clock in frequency multiplier with reference to the benchmark jitter analysis of the multiphase clock counterpart using conventional delay-locked loop (DLL) approach. The analysis results have shown that the jitter performance of PPF-based design is better than that of DLL-based design. Jitter measurement on the PPF-based multiphase clock chip has been conducted. The overall comparison has shown excellent agreement among prediction results from theory and realistic simulation results from a combination of all the transistor-level circuits in conjunction with the proposed behavioral model. The comparison results confirm the proposed time domain jitter analysis method. The results have shown that not only do the PPF-based demonstrate the improved jitter performance, the deterministic jitter performance is also independent of components mismatch. Finally, the practical measurement results of the fabricated chip identifies the practical pitfalls of the proposed PPF-based DLL design, suggesting further jitter reduction and demonstrating the potential low-jitter design using the PPF-based DLL.