Analysis of the spur characteristics of edge-combining DLL-based frequency multipliers
IEEE Transactions on Circuits and Systems II: Express Briefs
Jitter analysis of polyphase filter-based multiphase clock in frequency multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a novel differential quadrature crystal oscillator
Analog Integrated Circuits and Signal Processing
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A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between ×6, ×3, and ×2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in the lock state, which is achieved by decreasing the charge-pump (CP) current during the idle interval of the phase detector. The proposed DLL frequency synthesizer, which has been realized in a CMOS 90-nm technology, consumes 20 mW at 1.2 V supply with the frequency-multiplied output covering from 0.45 to 5.4 GHz. For 850-MHz input clock, the phase noise at 1-MHz frequency offset after ×6, ×3, and ×2 is -121.4, -127.4, and -129.7 dBc/Hz, respectively. The corresponding output spurs achieve -26.2, -36.8, and -39.2 dBc for ×6, ×3, and ×2, which are 7.6, 5.9, and 15.4 dB lower than those using a conventional current-steering CP, respectively.