Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop
IEEE Transactions on Circuits and Systems II: Express Briefs
A programmable edge-combining DLL with a current-splitting charge pump for spur suppression
IEEE Transactions on Circuits and Systems II: Express Briefs
Classical and modern receiver architectures
IEEE Communications Magazine
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A novel crystal oscillator circuit with differential quadrature outputs is presented in this paper. It couples two differential Pierce structures with an annular cascade structure to realize differential quadrature outputs directly. A prototype of the circuit was fabricated in SMIC 0.18 μm CMOS process technology. The measurement results show that the maximum quadrature phase mismatch of adjoining signals is lower than 1.3° and the maximum amplitude mismatch is less than 1 %. Compared to the conventional quadrature signal implementations such as poly phase filter network, or a current mode logic divider, our proposed circuit can directly achieve differential quadrature outputs with much better phase noise and excellent differential quadrature matching. It proves potential application prospect in many radio frequency transceiver systems which require rigorous matching characteristics of differential quadrature local oscillator for excellent performance of image rejection.