Lattice basis reduction: improved practical algorithms and solving subset sum problems
Mathematical Programming: Series A and B
Error Control Coding, Second Edition
Error Control Coding, Second Edition
A radius adaptive K-Best decoder with early termination: algorithm and VLSI architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
Design and implementation of a sort-free K-best sphere decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
Hi-index | 0.00 |
This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4×4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW.