Lattice basis reduction: improved practical algorithms and solving subset sum problems
Mathematical Programming: Series A and B
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
An adaptive reduced complexity K-best decoding algorithm with early termination
CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
A radius adaptive K-Best decoder with early termination: algorithm and VLSI architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools
Analog Integrated Circuits and Signal Processing
High-throughput soft-output MIMO detector based on path-preserving trellis-search algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A best-first soft/hard decision tree searching MIMO decoder for a 4×4 64-QAM system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes the design and very-large-scale integration (VLSI) architecture for a 4 × 4 breadth-first K-best multiple-input-multiple-output (MIMO) decoder using a 64 quadrature-amplitude modulation (QAM) scheme. A novel sort-free approach to path extension, as well as quantized metrics result in a high-throughput VLSI architecture with lower power and area consumption compared to state-of-the-art published systems. Functionality is confirmed via a field-programmable gate array (FPGA) implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given, and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized application-specific IC (ASIC) implementation in a 65-nm CMOS technology.