C Based Hardware Design for Wireless Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
High-Level Synthesis: Past, Present, and Future
IEEE Design & Test
Impulse C vs. VHDL for Accelerating Tomographic Reconstruction
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector
Proceedings of the Conference on Design, Automation and Test in Europe
Design and implementation of a sort-free K-best sphere decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems
Journal of Signal Processing Systems
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In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL's AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz. The obtained results show that these modern HLS tools produce Quality of Results competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.