Communicating sequential processes
Communicating sequential processes
A hierarchy of temporal properties (invited paper, 1989)
PODC '90 Proceedings of the ninth annual ACM symposium on Principles of distributed computing
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Patterns in property specifications for finite-state verification
Proceedings of the 21st international conference on Software engineering
Formal verification of parallel programs
Communications of the ACM
Software Engineering: A Practitioner's Approach
Software Engineering: A Practitioner's Approach
Automated Software Engineering
Using the Bandera Tool Set to Model-Check Properties of Concurrent Java Software
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
International Journal on Software Tools for Technology Transfer (STTT) - Special section on high-level test of complex systems
Formal Verification of Protocol Properties of Sequential Java Programs
COMPSAC '07 Proceedings of the 31st Annual International Computer Software and Applications Conference - Volume 01
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
jStar: towards practical verification for java
Proceedings of the 23rd ACM SIGPLAN conference on Object-oriented programming systems languages and applications
ICTSS'10 Proceedings of the 22nd IFIP WG 6.1 international conference on Testing software and systems
Polyglot: modeling and analysis for multiple Statechart formalisms
Proceedings of the 2011 International Symposium on Software Testing and Analysis
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Software formal verification is a technique used to ensure that computational systems have high-quality and work properly. From the system specification described in a formal language, we define properties that must be satisfied during system execution to guarantee the software quality. Then, these properties should be implemented in a verifier, tool responsible for running the verification and for notifying which properties were satisfied or not. When the verification process finishes, the verifier will indicate to software developers the possible location of each code fault in the system. The disadvantages of using formal verification are the high cost to apply this technique in real systems, and the necessity of having people with experience in formal languages and formal methods. In addition, the implementation of properties related to a particular system in a verifier is a complex task. To help software developers in the application of formal verification in Java programs, this work proposes the generation of properties code, for direct use in a verifier, from test purposes derived from system formal requirements.