Architecting a common-source-line array for bipolar non-volatile memory devices

Authors:
Bo Zhao;Jun Yang;Youtao Zhang;Yiran Chen;Hai Li
Affiliations:
University of Pittsburgh;University of Pittsburgh;University of Pittsburgh;University of Pittsburgh;Polytechnic Inst. of NYU
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 1
Cited 1

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STT-RAM designs supporting dual-port accesses

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Abstract

Traditional array organization of bipolar non-volatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper we propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. We also elaborate our design flow towards a reliable common-source-line array design, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays. Our study results show that with comparable latency and energy, the proposed common-source-line array can save 33% and 21.8% area for Memristor-RAM and STT-MRAM respectively, comparing with corresponding traditional dual-bitline array designs.