Scaling towards kilo-core processors with asymmetric high-radix topologies

  • Authors:

  • Nilmini Abeyratne;Reetuparna Das;Qingkun Li;Korey Sewell;Bharan Giridhar;Ronald G. Dreslinski;David Blaauw;Trevor Mudge

  • Affiliations:

  • Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA

  • Venue:
  • HPCA '13 Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
  • Year:
  • 2013

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Abstract

In this paper, we explore the challenges in scaling on-chip networks towards kilo-core processors. Current low-radix topologies optimize for fast local communication, but do not scale well to kilo-core systems because of the large number of routers required. These increase both power and hop count. In contrast, symmetric high-radix topologies optimize for global communication with fewer hop counts, but degrade local communication with their large, slow routers.