Smart memory architecture and methods
Future Generation Computer Systems
Imperative functional programming
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Content Addressable Parallel Processors
Content Addressable Parallel Processors
Purely Functional Data Structures
Purely Functional Data Structures
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Data Parallel Implementation of Extensible Sparse Functional Arrays
PARLE '93 Proceedings of the 5th International PARLE Conference on Parallel Architectures and Languages Europe
Stretching the Storage Manager: Weak Pointers and Stable Names in Haskell
IFL '99 Selected Papers from the 11th International Workshop on Implementation of Functional Languages
ICSE '81 Proceedings of the 5th international conference on Software engineering
A memory system design framework: creating smart memories
Proceedings of the 36th annual international symposium on Computer architecture
Accelerating Haskell array codes with multicore GPUs
Proceedings of the sixth workshop on Declarative aspects of multicore programming
Massively parallel breadth first search using a tree-structured memory model
Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores
Compiling CHR to parallel hardware
Proceedings of the 14th symposium on Principles and practice of declarative programming
Shared hardware data structures for hard real-time systems
Proceedings of the tenth ACM international conference on Embedded software
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A longstanding open question in algorithms and data structures is the time and space complexity of pure functional arrays. Imperative arrays provide update and lookup operations that require constant time in the RAM theoretical model, but it is conjectured that there does not exist a RAM algorithm that achieves the same complexity for functional arrays, unless restrictions are placed on the operations. The main result of this paper is an algorithm that does achieve optimal unit time and space complexity for update and lookup on functional arrays. This algorithm does not run on a RAM, but instead it exploits the massive parallelism inherent in digital circuits. The algorithm also provides unit time operations that support storage management, as well as sparse and extensible arrays. The main idea behind the algorithm is to replace a RAM memory by a tree circuit that is more powerful than the RAM yet has the same asymptotic complexity in time (gate delays) and size (number of components). The algorithm uses an array representation that allows elements to be shared between many arrays with only a small constant factor penalty in space and time. This system exemplifies circuit parallelism, which exploits very large numbers of transistors per chip in order to speed up key algorithms. Extensible Sparse Functional Arrays (ESFA) can be used with both functional and imperative programming languages. The system comprises a set of algorithms and a circuit specification, and it has been implemented on a GPGPU with good performance.