| Hi-index | 0.00 |
Data-rate of wireless links are increasing fast, particularly when new carrier bands with very high bandwidth becomes available. Utilizing the full bandwidth for a single carrier facilitates very large baud-rates. When the baud-rates approaches or exceeds Gbaud, the implementation of the digital baseband is no longer a simple extension of existing methods. In the present paper we propose a resource efficient implementation of digital baseband for multi-Gbaud rates in a standard FPGA utilizing Xilinx Simulink-based System generator design and verification tool.