Fundamentals of algorithmics
Optimal and Practical Algorithms for Sorting on the PDM
IEEE Transactions on Computers
Proceedings of the VLDB Endowment
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study
IEEE Transactions on Computers
On Sorting, Heaps, and Minimum Spanning Trees
Algorithmica
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Implementation in FPGA of Address-Based Data Sorting
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
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Among numerous data processing tasks sorting is considered to be one of the most important. Sorting still poses a big challenge as it actually becomes harder to solve this problem efficiently and fast with the constant demand for processing of larger and larger data sets in a reasonable amount of time. Reconfigurable computing provides an attractive option for implementation of data processing in the context of hardware, as the use of Field Programmable Gate Arrays (FPGAs) allows to eliminate the design constraints of processors and graphics processing units (GPUs) with predefined architectures. In this paper a technique that improves the performance of the address-based data sorting unit with an external DDR3 flag memory is proposed. It is demonstrated that the proposed technique can efficiently reduce the communication penalties associated with the use of external memory.