Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Leakage Aware Feasibility Analysis for Temperature-Constrained Hard Real-Time Periodic Tasks
ECRTS '09 Proceedings of the 2009 21st Euromicro Conference on Real-Time Systems
Leakage conscious DVS scheduling for peak temperature minimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
TempoMP: integrated prediction and management of temperature in heterogeneous MPSoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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With exponentially increased transistor density on multi-core platforms, the power explosion and consequently soaring chip temperature have become critical challenges for system designers. Moreover, the increasing chip temperature results in higher leakage power, hence further aggravates the increment of the overall power consumption [1]. Thus, the dramatically growing power/energy consumption and chip temperature severely affect the cost, reliability and performance of the systems [4].