Packet Classification Using Extended TCAMs
ICNP '03 Proceedings of the 11th IEEE International Conference on Network Protocols
Algorithms for advanced packet classification with ternary CAMs
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
DRES: Dynamic Range Encoding Scheme for TCAM Coprocessors
IEEE Transactions on Computers
High-Speed Packet Classification with Efficient Parallel Range Match for IP Network Applications
MMIT '08 Proceedings of the 2008 International Conference on MultiMedia and Information Technology
A high-speed and EDP-efficient range-matching scheme for packet classification
IEEE Transactions on Circuits and Systems II: Express Briefs
A high-speed range-matching TCAM for storage-efficient packet classification
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Space-Efficient TCAM-Based Classification Using Gray Coding
IEEE Transactions on Computers
Efficient Multimatch Packet Classification for Network Security Applications
IEEE Journal on Selected Areas in Communications
Algorithms for packet classification
IEEE Network: The Magazine of Global Internetworking
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This article introduces a high-performance packet filter design in which we propose the partial parallel range check (PPRC) technique for speeding up port range check. Unlike the conventional serial design that uses cascading cells to perform the serial check, PPRC divides the single path into several segments. All PPRC segments perform the range compare simultaneously, that is, parallel check, and then the results of each segment are serialized to generate the final check result. Besides theoretical analyses, we also use UMC 90nm CMOS process to implement the PPRC design and verify its effect on the check performance. Compared to state-of-the-art range check techniques, the results show that the PPRC design with the best configuration can improve check performance by 28%, at least. In addition, the PPRC design is more stable and energy efficient than related designs, even though it requires more transistors to implement the peripheral circuitry. The range of energy improvement achieved by the PPRC design is about 35%--70%.