Direct-mapped versus set-associative pipelined caches

Reducing the cost of branches

ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture

Cache design of a sub-micron CMOS system/370

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture

Cache Operations by MRU Change

IEEE Transactions on Computers

A Case for Direct-Mapped Caches

Computer

Evaluating Associativity in CPU Caches

IEEE Transactions on Computers

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach

Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers

IEEE Transactions on Computers

Alternative implementations of two-level adaptive branch prediction

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture

Performance optimization of pipelined primary cache

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture

Tradeoffs in two-level on-chip caching

ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture

Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture

A study of branch prediction strategies

ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture

Aspects of cache memory and instruction buffer performance

Aspects of cache memory and instruction buffer performance