Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code

High-bandwidth data memory systems for superscalar processors

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems

Tradeoffs in processor/memory interfaces for superscalar processors

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture

Compile-time parallelization of non-numerical code: VLIW superscalar

Compile-time parallelization of non-numerical code: VLIW superscalar

Two-ported cache alternatives for superscalar processors

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture

A study on the number of memory ports in multiple instruction issue machines

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture