Guided region prefetching: a cooperative hardware/software approach
Proceedings of the 30th annual international symposium on Computer architecture
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Increasing PCM main memory lifetime
Proceedings of the Conference on Design, Automation and Test in Europe
MN-Mate: Resource Management of Manycores with DRAM and Nonvolatile Memories
HPCC '10 Proceedings of the 2010 IEEE 12th International Conference on High Performance Computing and Communications
Migration based page caching algorithm for a hybrid main memory of DRAM and PRAM
Proceedings of the 2011 ACM Symposium on Applied Computing
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As DRAM-based main memory becomes a dominant factor in the energy consumption and cost of any computer system, new non-volatile memory technologies have been proposed to replace DRAMs. For example, PRAM is emerged as a leading alternative for main memory technology. However, the access latency of PRAM is significantly slower than that of DRAM and an interfacing converter is required to at least partly alleviate this latency difference. The interfacing converter sits between PRAM-based main memory and the last level of cache memory. In this paper, we present a proposed dynamic adaptive converter and its management scheme for PRAM-based main memory. In addition to overcoming long access latency, it provides enhanced endurance. The adaptive converter is composed of an aggressive streaming buffer to make better use of spatial locality by dynamically varying fetch size, a write buffer to improve endurance limit, and an adaptive filtering buffer to better utilize temporal locality. Our experimental results show that we can reduce buffer miss rate by about 59%, compared with using a single buffer structure with same space. Our approach also hides PRAM access latency more effectively. It improves the number of superblocks pre-fetched from main memory by 25%. Therefore, the converter shows its effectiveness comparable to a case with larger buffer space, without expending the extra power.