Phase-change random access memory: a scalable technology
IBM Journal of Research and Development
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
FSAF: file system aware flash translation layer for NAND flash memories
Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Age-based PCM wear leveling with nearly zero search cost
Proceedings of the 49th Annual Design Automation Conference
Working-set-based address mapping for ultra-large-scaled flash devices
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Adaptive page grouping for energy efficiency in hybrid PRAM-DRAM main memory
Proceedings of the 2012 ACM Research in Applied Computation Symposium
Energy efficient caching for phase-change memory
MedAlg'12 Proceedings of the First Mediterranean conference on Design and Analysis of Algorithms
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
ACM Transactions on Architecture and Code Optimization (TACO)
Reducing writes in phase-change memory environments by using efficient cache replacement policies
Proceedings of the Conference on Design, Automation and Test in Europe
Software enabled wear-leveling for hybrid PCM main memory on embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing video application design for phase-change RAM-based main memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Writeback-aware bandwidth partitioning for multi-core systems with PCM
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
A dynamic adaptive converter and management for PRAM-based main memory
Microprocessors & Microsystems
ARI: Adaptive LLC-memory traffic management
ACM Transactions on Architecture and Code Optimization (TACO)
Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS)
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The introduction of Phase-Change Memory (PCM) as a main memory technology has great potential to achieve a large energy reduction. PCM has desirable energy and scalability properties, but its use for main memory also poses challenges such as limited write endurance with at most 107 writes per bit cell before failure. This paper describes techniques to enhance the lifetime of PCM when used for main memory. Our techniques are (a) writeback minimization with new cache replacement policies, (b) avoidance of unnecessary writes, which write only the bit cells that are actually changed, and (c) endurance management with a novel PCM-aware swap algorithm for wear-leveling. A failure detection algorithm is also incorporated to improve the reliability of PCM. With these approaches, the lifetime of a PCM main memory is increased from just a few days to over 8 years.