Optimal networks from error correcting codes

  • Authors:
  • Ratko V. Tomic

  • Affiliations:
  • Infinetics Technologies, Inc., Boston, MA, USA

  • Venue:
  • ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
  • Year:
  • 2013

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Abstract

To address growth challenges facing large Data Centers and supercomputing clusters a new construction is presented for scalable, high throughput, low latency networks. The resulting networks require 1.5-5 times fewer switches, 2-6 times fewer cables, have 1.2-2 times lower latency and correspondingly lower congestion and packet losses than the best present or proposed networks providing the same number of ports at the same total bisection. These advantage ratios increase with network size. The key new ingredient is the exact equivalence discovered between the problem of maximizing network bisection for large classes of practically interesting Cayley graphs and the problem of maximizing codeword distance for linear error correcting codes. Resulting translation recipe converts existent optimal error correcting codes into optimal throughput networks. Ethernet implementation was developed and a prototype built using managed COTS switches. Integrated control plane handles topology, distribution of forwarding tables and fault recovery. Scalable routing uses stretch-free topological addressing. Local load balancing distributes flows at the source over multiple, non-minimal, edge disjoint paths. Path selection does not use tunneling or overlays but embeds path selectors in the topological addresses resulting in wire-speed forwarding and allowing for cut-through switching where available.