Mechanism of synchronization in frequency dividers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On the theory of quadrature oscillations obtained through parallel LC VCOs
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
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Divide-by-three frequency dividers with direct forcing signal are analyzed, and the actual locking mechanism underlying their operation is highlighted. In particular, it is shown that the lockingmechanism cannot be explained with the mixing between signals, as commonly made in the literature. An analytical procedure based on the averaging method is developed for solving the equation describing such dividers, and the first approximation to the oscillation in the locked states is predicted. The amplitude and phase of the output voltage in steady state as well as the locking range are derived in terms of the circuit parameters, obtaining useful design guidelines. The derived results are shown to be very close to SPICE simulations for a 0.13 um RF-CMOS process.