Systematic analysis and cancellation of kickback noise in a dynamic latched comparator

  • Authors:

  • Ka-Meng Lei;Pui-In Mak;Rui P. Martins

  • Affiliations:

  • State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China;State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China;State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China and Instituto Superior Técnico, U of Lisbon, Lisbon, Portugal

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2013

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Abstract

A dynamic latched comparator can suffer from three non-idealities: offset voltage, random noise and kickback noise. Specifically in an analog-to-digital converter (ADC) the kickback noise of a comparator can noticeably affect the settling time and accuracy of the decision. This work offers an analytical treatment of kickback noise generation, and proposes a synchronized kickback noise cancellation technique, which is achieved via placing clocked NMOS-PMOS capacitors at the proper nodes to cancel out effectively those unwanted charges (electrons or holes) under different operating regions of the MOS devices. The technique is clock-rate insensitive and particularly suitable for the SAR-type ADC as it will not alter the charge stored in the capacitor array. Optimized in 65-nm CMOS the kickback noise is pp, the kickback noise of the proposed comparator comparing with the conventional one is improved by 48脳, from 6.27 to 0.13 LSB.