Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors

Authors:
M. Kotti;R. González-Echevarría;F. V. Fernández;E. Roca;J. Sieiro;R. Castro-López;M. Fakhfakh;J. M. López-Villegas
Affiliations:
University of Sfax, Sfax, Tunisia;Institute of Microelectronics of Seville (IMSE-CNM), CSIC and University of Seville, Seville, Spain 41092;Institute of Microelectronics of Seville (IMSE-CNM), CSIC and University of Seville, Seville, Spain 41092;Institute of Microelectronics of Seville (IMSE-CNM), CSIC and University of Seville, Seville, Spain 41092;Grup de Radiofreqüència, Facultat de Física, Universitat de Barcelona, Barcelona, Spain 08028;Institute of Microelectronics of Seville (IMSE-CNM), CSIC and University of Seville, Seville, Spain 41092;University of Sfax, Sfax, Tunisia;Grup de Radiofreqüència, Facultat de Física, Universitat de Barcelona, Barcelona, Spain 08028
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2014

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Abstract

Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-μm CMOS technology are provided.